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Explore Inside the AI Hardware Engine – Full Semiconductor Supply Chain Course with 204,214 views, 2,114 likes, and 159 comments. Experience the impact of this video content that has captured audience attention.

Welcome to this comprehensive course on the semiconductor supply chain, where you will learn how a chip moves from design to the data center. You will learn all about semiconductor physics, design, fabrication, memory, packaging, and rack-scale integration. Your instructor, Kian, will guide you through this journey to help you understand the hardware infrastructure powering modern artificial intelligence. Course created by @neuralkian Course info: https://github.com/kiankyars/chips ❤️ Support for this channel comes from our friends at Scrimba – the coding platform that's reinvented interactive learning: https://scrimba.com/freecodecamp ⭐️ Chapters ⭐️ - 0:00:00 Intro & Course Overview - 0:04:21 GB300 Architecture & Scale-Up vs. Scale-Out - 0:08:44 Reticle Limits, Dual Dies & NV-HBI - 0:11:00 High Bandwidth Memory (HBM) - 0:13:28 Caches, NVLink & PCIe Routing - 0:16:15 Inference Walkthrough & Memory Hierarchy - 0:19:55 Hardware Economics & Transistor Budgets - 0:22:41 Vera Rubin & Next-Gen Roadmap - 0:24:46 Part 1: Semiconductor Physics - 0:26:07 Logic vs. Memory & Clock Speeds - 0:28:34 1T1C DRAM Cells, SRAM & 3D TSVs - 0:30:14 Transistor Basics & Scaling History - 0:32:46 What Process Nodes Mean (PPA) - 0:35:28 Planar, FinFET & Gate-All-Around - 0:40:50 End of Dennard Scaling - 0:42:04 Rock’s Law & Fab Economics - 0:43:40 The Great Unbundling: Fabless & Foundries - 0:45:44 4 Modern Semiconductor Business Models - 0:47:16 Part 2: Chip Design & EDA - 0:48:24 SMs, Tensor Cores & Parallelism - 0:50:39 CUDA: The Software Moat - 0:52:16 Nvidia Margins & Market Dominance - 0:53:14 The EDA Flow: RTL to Tape-Out - 0:55:46 Leading-Edge Design Costs - 0:56:56 Synopsys, Cadence & Siemens EDA - 1:00:16 Choke Point #1: Certified EDA Tools - 1:01:00 EDA Export Controls - 1:02:22 Semiconductor IP: ARM vs. RISC-V - 1:04:47 ARM's Move into Custom Silicon - 1:06:59 Fabless: Merchant, In-House & Custom ASICs - 1:08:49 Part 3: Foundries & Manufacturing - 1:10:30 History of TSMC & Morris Chang - 1:12:15 Die Size, Defect Density & Yield Models - 1:14:56 The Fab Scale Flywheel & Capex - 1:16:33 How Apple De-Risked Node Ramps - 1:18:49 5 Pillars of a Dependable Foundry - 1:20:09 TSMC Roadmaps (N2, A16) & High-NA EUV - 1:22:21 Wafer Pricing Trends - 1:23:06 Choke Point #2: Leading-Edge Foundry Capacity - 1:25:20 Geographic Concentration & TSMC Global Fabs - 1:26:23 The Fall & Restructuring of Intel - 1:31:32 Intel 18A / 14A Turnaround Plan - 1:34:56 Rapidus, SMIC & Global Foundry Frontier - 1:36:23 Wafer Fab Equipment (WFE) Overview - 1:37:16 Silicon Ingots & Spruce Pine Quartz - 1:38:21 Photomasks & Reticle Costs - 1:40:27 Inside the Fab: Building a Wafer Layer - 1:44:17 Doping & Annealing - 1:45:51 Inline Inspection & Wafer Travel - 1:48:08 Why Wafer Cycles Take 3–4 Months - 1:50:41 Cleanroom Standards: ISO 1 Air - 1:51:56 ASML & High-NA EUV Colossus - 1:53:14 Optical Columns & Carl Zeiss Mirrors - 1:56:34 The Extreme Supply Chain Behind EUV - 1:58:10 Numerical Aperture & Resolution Limits - 2:00:00 3D NAND Stacking & High Aspect Etch - 2:01:00 Applied Materials, Lam Research & TEL - 2:04:56 Metrology & Inspection: KLA’s Moat - 2:07:54 Choke Point #3: Japanese Materials - 2:10:06 Material Shocks: Neon, Quartz & Embargoes - 2:11:51 The Other 90%: Legacy Nodes & Auto Shortages - 2:13:21 Part 4: Memory Cycles & HBM - 2:14:35 DRAM Economics & Supplier History - 2:17:03 The AI Memory Wall - 2:18:02 HBM3E Specs & TSV Wafer Penalty - 2:20:56 Part 5: Advanced Packaging & Interconnect - 2:22:34 Anatomy of CoWoS-L - 2:24:58 Choke Point #4: Advanced Packaging - 2:26:02 NVLink, NV-Switch Trays & SuperNICs - 2:27:14 Part 6: Geopolitics & Policy Risk - 2:28:20 Escalation of US-China Export Controls - 2:29:30 Nvidia’s Access to China - 2:30:20 Collateral Impact: Automotive Mature Nodes - 2:31:50 China's Counter-Strategy: Yield vs. Power - 2:32:40 Tooling & Domestic Supply Chain Gaps - 2:33:40 Taiwan Conflict Scenarios & Economic Impact - 2:34:20 Diverging AI Hardware Stacks - 2:35:20 Rack-Scale Power Limits (135 kW) - 2:36:00 Conclusion: Core Supply Chain Choke Points 🎉 Thanks to our Champion and Sponsor supporters: 👾 @omerhattapoglu1158 👾 @goddardtan 👾 @akihayashi6629 👾 @kikilogsin 👾 @anthonycampbell2148 👾 @tobymiller7790 👾 @rajibdassharma497 👾 @CloudVirtualizationEnthusiast 👾 @adilsoncarlosvianacarlos 👾 @martinmacchia1564 👾 @ulisesmoralez4160 👾 @_Oscar_ 👾 @jedi-or-sith2728 👾 @justinhual1290 -- Learn to code for free and get a developer job: https://www.freecodecamp.org Read hundreds of articles on programming: https://freecodecamp.org/news

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